One prior computer system, the PC/XT computer system, has an interrupt controller coupled to eight interrupt request lines. The eight interrupt request lines are in turn coupled to peripheral devices or other components. The interrupt controller is also coupled to a microprocessor by a single interrupt signal line. When the interrupt controller receives an interrupt request signal over one of the eight interrupt request lines from a peripheral device or other device, it transmits an interrupt signal to the microprocessor over the single interrupt signal line. Thus, every interrupt request signal regardless of the source results in the transmission of the same interrupt signal to the microprocessor.
A second prior computer system, the PC/AT computer system, has two interrupt controllers. The first interrupt controller is coupled to a microprocessor by a single interrupt line. The first interrupt controller is also coupled to eight interrupt request lines. Seven of the eight interrupt request lines are coupled to peripheral or other components. The eighth interrupt request line is coupled to the second interrupt controller. The second interrupt controller is in turn coupled to another eight interrupt request lines. The eight interrupt request lines are coupled to peripheral or other components. In this manner, a total of fifteen interrupt request lines are provided for use by peripheral or other components.
When the first interrupt controller receives an interrupt request signal over one of the seven interrupt request lines from a peripheral device or other device, it transmits an interrupt signal to the microprocessor over the single interrupt signal line. Thus, every interrupt request signal on any of the seven interrupt request lines regardless of the source results in the transmission of the same interrupt signal to the microprocessor. In addition, when the second interrupt controller receives an interrupt request signal over one of its eight interrupt request lines from a peripheral device or other device, it transmits an interrupt request signal to the first interrupt controller. The first interrupt controller in response to the interrupt request signal from the second interrupt controller transmits an interrupt signal to the microprocessor over the single interrupt signal line. Thus, every interrupt request signal on any of the eight interrupt request lines of the second controller regardless of the source results in the transmission of the same interrupt request signal to the first interrupt controller and the same interrupt signal to the microprocessor.
In the PC/AT computer system, when the microprocessor receives an interrupt signal, it queries the first interrupt controller to determine the source of the interrupt signal. In querying the first interrupt controller, all eight interrupt request lines of the first interrupt controller are polled. If the interrupt signal originated due to an interrupt request signal on the eighth interrupt request line of the first interrupt controller, the microprocessor also queries the second interrupt controller. In querying the second interrupt controller, all eight interrupt request lines of the second interrupt controller are polled. In this manner, the microprocessor can determine which of the fifteen interrupt request lines caused the interrupt signal to the microprocessor and thus, can determine the source of the interrupt signal.
However, the PC/AT computer system is limited to fifteen interrupt request lines. With the expansion of computer systems to incorporate additional functionalities e.g. audio, video and multimedia, additional interrupt handling capacity is required to achieve a requisite level of performance.
Thus, an interrupt request router that provides enhanced interrupt request handling capability is needed.